1. Field of Invention
This invention relates to semiconductor memory and, more particularly, to test and repair of semiconductor memory.
2. Description of Related Art
Testing an integrated circuit can be performed in various ways. For example, the integrated circuit can be tested while in wafer form using test probe operation. additionally, or alternatively, the integrated circuit can be tested after it is scribed and packaged. In either instance, sequential and/or combinatorial logic of the integrated circuit must be tested using input test data, generally referred to as xe2x80x9ctest vectors.xe2x80x9d Test vectors are supplied from a commercial test machine or Automated Test Equipment (xe2x80x9cATExe2x80x9d). Alternatively, the test vectors can be provided from circuitry upon the integrated circuit. Such circuitry is often referred to as built in self test (xe2x80x9cBISTxe2x80x9d) circuitry. BIST circuitry may use a pseudo-random sequence generator to produce test vectors forwarded to the functional core logic of the integrated circuit.
As semiconductor technology has advanced, making possible higher levels of integration, device testability has become increasingly problematic. Semiconductor manufacturers have resorted to higher pin counts and smaller pin separations on device packages, in order to accommodate very highly integrated circuits. It is no longer feasible in some cases to probe these integrated circuits externally, because of the minute physical dimensions of the package leads. Furthermore, device operating speeds have also increased to the point where loading and introduction of noise by external probes has become an important consideration.
A further disadvantage to the use of conventional external device testers arises when the memory under test is xe2x80x9cembeddedxe2x80x9dxe2x80x94i.e., the memory is a component within a more complex integrated circuit. The embedded memory is often present in the form of on-chip RAM within an application specific integrated circuit (ASIC). Frequently, there is intervening circuitry between the memory device and the input/output (I/O) pins on the device package. In such cases, many of the memory signal ports are not externally accessible. The device tester is then incapable of probing the memory directly.
Traditional methods of testing rely on external test equipment, such as oscilloscopes and logic analyzers. Often, huge numbers of test cases must be evaluated to fully validate a sophisticated integrated device, and the amount of time required for a human tester to administer a full suite of tests becomes prohibitive. Automated Test Equipment (ATE) can often be employed to test such complex devices, but is expensive and time-consuming to set up. Therefore, the use of automated testers is largely limited to the production environment. Furthermore, for many high-performance integrated circuits, even an automated tester may not be feasible. For instance, some processors operate at such high clock rates that it is virtually impossible to maintain the integrity of data and control signals over the distance separating the IC and the tester. For these, and other reasons, much of the test functionality has been moved into the integrated circuit itself.
An important development that has arisen out of the need to test ever more complex integrated circuits, is the introduction of boundary scan test capability. Boundary scan testing requires the inclusion of diagnostic circuitry with the core logic of the device under test. Among this diagnostic circuitry is a boundary scan register, which functions analogously to a parallel-in/parallel-out shift register. The scan register is capable of applying diagnostic bit patterns (xe2x80x9ctest vectorsxe2x80x9d) to the inputs of the core logic, and capturing the resulting state of core logic outputs. The boundary scan test circuitry may share the same die as the integrated circuit itself. Alternatively, the test circuitry may be on a different die, but within the same package as the circuit itself. With the test circuitry in such close proximity, the difficulty in monitoring and controlling high-speed signals is reduced. A simplified external tester communicates with the boundary scan test circuitry, and has only to initiate tests and collect the results.
Boundary scan test techniques have been successfully applied in semiconductor memory devices. However, the conventional approach requires adding significant test circuitry to the memory device, as well as additional I/O pins on the device package dedicated to test functions. When the memory is embedded, the addition of the boundary scan test circuitry may be problematic. In the first place, the test circuitry may require considerable additional area on the semiconductor die, leading to placement and routing difficulties. Furthermore, since the exact location of the test circuit elements and the associated signal path lengths cannot generally be known in advance, the timing characteristics of the scan-enabled memory are not readily predictable. To ensure adequate performance and reliability, a rigorous reevaluation of the timing parameters for the embedded memory device may be required.
It would be desirable to incorporate boundary scan test circuitry into an embedded memory device, while avoiding the disadvantages described above. Preferably, a minimum of additional circuitry would be required, and its inclusion would not influence the timing parameters of the memory device itself. Ideally, the boundary scan test circuitry could be used with various types of embedded memoryxe2x80x94e.g., SRAM, CAM, etc. It would be of further advantage if the interface did not require the addition of a large number of device pins to the integrated circuit package.
Testing of embedded semiconductor memory devices is made difficult by the fact that many of the device signal ports are not externally accessible. Therefore, testing is often accomplished using boundary scan circuitry, incorporated on the same semiconductor die as the memory. However, the inclusion of such circuitry has some drawbacks. In the first place, the boundary scan test circuitry can occupy considerable additional die area. This may make layout and routing of the integrated circuit much more difficult. Furthermore, if the boundary scan components are inserted into the signal paths of the memory device they will influence critical timing parameters, and may degrade device performance.
Disclosed herein is a system for providing scan testability in an embedded memory device, which overcomes the above problems. In an embodiment of the system disclosed herein, complementary half-latches are added to already-existing half-latches at the signal inputs of the embedded memory device. Each pair of half-latches operates as a full-latch. Dual-input multiplexers at the input of each full-latch select between the nominal signal and a scan test signal, which is the output of the previous full-latch. This allows the full-latches to be connected in parallel or in series. The parallel configuration corresponds to functional (i.e., normal) operation of the memory, while the series configuration supports scan testing of the memory and associated circuitry. A scan control signal programs the multiplexers to select between the functional and the test configuration.
Advantageously, the system disclosed herein isolates the normal signal path from the scan path during normal operation. Accordingly, each functional input signal (e.g., address, data) traverses only the already-existing half-latch, and not the complementary one as well. This avoids the increased propagation time that would result from having the signal pass through two latches. A further advantage results from the fact that the additional logic required for scan testability resides within the memory device itself. This reduces the difficulty for the memory designer of placing and routing the scan circuitry. The system disclosed herein is believed to be applicable to embedded memory devices of various types, such as static dynamic random access memory (SRAM) or content addressable memory (CAM).
A method for incorporating scan testability in an embedded memory is also disclosed herein. According to this method, the memory supports operation in either functional or test mode, and a pair of half-latches is associated with each of the functional input signals directed to the memory. In the functional mode, the primary half-latch in each pair of half-latches captures a respective bit from the input signal, and drives the stored value upon a corresponding functional signal line within the memory. In the test mode, the pairs of primary and secondary half-latches are connected in series, such that the output of the secondary half-latch in a given pair conveys its stored value to the input of the primary half-latch of the next pair. Thus, the scan input signal presented to the input of the primary half-latch in the first pair propagates through all the pairs, in the manner of a shift register, emerging as a scan output signal from the final pair. A scan control signal is used to configure the half-latches for functional or test mode operation.